1. Field of the Invention
The present invention relates to a reference voltage generator for semiconductor devices, and more particularly to a circuit for generating the reference voltage whose level is capable of being minutely trimmed by the anti-fuse programming.
2. Description of the Prior Art
Recently, a reference voltage generator is used in a DRAM according to it being rapid in its precessing speed, and having a lower power consumption, and bing more highly integrated, wherein the reference voltage may be easily varied by the changes in a temperature, an external voltage, or a fabrication process.
To minimize the variation in response to the changes of the external environments, the reference voltage generator typically includes a minutely trimming circuit in order to adjust the level of the reference voltage.
FIG. 1 is a block diagram showing the conventional reference voltage generator. With reference to this drawing, the conventional reference voltage generator comprises a reference voltage generation unit 1 for generating a reference voltage Vref having a predetermined level, and a decoding unit 2 for generating signals s0 to s7 and s0b to s7b in response to the blowing of the fuses included therein so that a voltage level to be changed is selected. The decoding unit 2 further comprises a voltage trimming unit 3 for amplifying the reference voltage Vref from the reference voltage generation unit 1 on the basis of the output signals s0 to s7 and s0b to s7b in order to output the trimmed reference voltage Vro1.
Typically, the first voltage generator 1 is provided with circuits such as a Widlar reference voltage generator or a band-gap reference voltage generator.
FIG. 2 is a detailed circuit diagram showing the decoding unit 2 of FIG. 1.
As shown in this drawing, the decoding unit 2 includes fuse units F1, F2 and F3 for receiving an external voltage Vext at their one sides to respectively generate signals rep1 and repb1, rep2 and repb2, and rep3 and repb3 according to their states . The decoding unit 2 further includes an output unit DOUT1 for logically combining the signals rep1 to rep3 and repb1 to repb3 in order to apply the signals s0 to s7 and inverted signals s0b to s7b thereof to the second voltage generator 3.
The output unit DOUT1 includes NAND gates NAND1 to NAND8 for receiving three of the signals rep1 to rep3 and repb1 to repb3 to outputting the inverted signals s0b to s7b, wherein the three signals have combinations different from each other, and inverters IN1 to IN8 for being connected respectively to the output terminals of the NAND gates NAND1 to NAND8, and generating the signals s0 to s7.
FIG. 3 is a detailed circuit diagram showing the fuse unit F1 in FIG. 2.
With reference to this drawing, the fuse unit F1 in the decoding unit 2 includes a charging unit 8 for being charged by the external voltage Vext applied via a fuse PF, and an output unit Fout for buffering the voltage charged in the charging unit 8 after being enabled thereby and then supplying the output unit DOUT1 with the signals rep1 and repb1. The fuse unit F1 further comprises a discharging unit 9 for being driven by the signal from the output unit FOUT, thereby completely discharging the voltage of the charging unit 8 when the fuse PF is blown.
The charging unit 8 and the discharging unit 9 are provided with a decoupling capacitor N8 and a N-channel MOS transistor N9, respectively.
The output unit FOUT includes inverters IN9, IN10 and IN11 for being enabled thereby and sequentially coupled to the charging unit 8, the discharging unit 9 and the fuse PF in common, wherein the output terminal of the inverter IN9 is also coupled to the gate of the N-channel MOS transistor N9 included in the discharging unit 9, and the inverters IN10 and IN11 generate the signals repb1 and rep1, respectively.
The fuse units F2 and F3 included in the decoding unit 2 are the same as the above mentioned fuse unit F1 in their constructions.
Hereinafter, the operation of the conventional reference voltage generator will be described in detail referring to the attached drawings.
As shown in FIG. 1, the reference voltage generation unit 1 generates the reference voltage Vref having a predetermined level, thereafter it adjusts the inputted reference voltage Vref in the case that it is changed according to the variations in the temperature around the semiconductor device or the process thereof. Namely, the voltage trimming unit 3 amplifies the reference voltage Vref on the basis of the signals s0 to s7 and s0b to s7b from the decoding unit 2, thereby generating the trimmed reference voltage Vro1.
With reference to FIG. 2, the decoding unit 2 logically combines the signals rep1 to rep3 and repb1 to repb3 from the fuse units F1, F2 and F3 to generate the signals s0 to s7.
As shown in FIG. 3, the fuse unit F1 generates the signals rep1 and repb1. At this time, the output signal from the inverter IN9 is applied to the gate of the N-channel MOS transistor N9 included in the charging unit 9. Therefore, the N-channel MOS transistor N9 is turned on in response to the high level signal from the inverter IN9 when the fuse PF is blown, thereby causing the voltage charged in the decoupling capacitor N8 to be discharged completely. At this time, the signal rep1 is pulled up to the high level, whereas the signal repb1 is pulled down to the low level.
In this manner, if at least one of the fuses is selectively blown in accordance with an operation state of the DRAM, the decoding unit 2 supplies the second voltage generator 3 with the signals s0 to s7 and s0b to s7b, after logically combining the signals rep1 to rep3 and repb1 to repb3.
The fuses included in the fuse units F1, F2 and F3 are made of poly-silicon and can be blown by a laser beam.
In the case of cutting polysilicon using a laser beam, this laser cutting method suffers from disadvantages such that an error may occur in accurately applying the laser beam to the polysilicon and a residue may remain around the disconnection part after the cutting. Another disadvantage of the laser cutting method is in that a large amount of processing time is required and it is difficult and inaccurate to perform the method. Further, the laser cutting method has another disadvantage such that it is impossible to trim the level of the reference voltage at a packaging process of the semiconductor device, resulting in a degradation in reliability of the semiconductor device, and in a relatively high cost thereof.